Changeset 2784d187 in ffmpeg

Timestamp:

Feb 23, 2012, 11:50:09 PM (13 years ago)

Author:

Ronald S. Bultje <rsbultje@gmail.com>

Branches:

master

Children:

6d110570

Parents:

34454c76

git-author:

Christophe GISQUET <christophe.gisquet@gmail.com> (02/23/12 19:12:39)

git-committer:

Ronald S. Bultje <rsbultje@gmail.com> (02/23/12 23:50:09)

Message:

SBR DSP x86: implement SSE sbr_hf_g_filt

Unrolling the main loop to process, instead of 4 elements:

• 8: minor gain of 2 cycles (not worth the extra object size)
• 2: loss of 8 cycles.

Assigning STEP to a register is a loss. Output address (Y) is almost always
unaligned.

Timings:

• C (32/64 bits): 117/109 cycles
• SSE: 57 cycles

Signed-off-by: Ronald S. Bultje <​rsbultje@gmail.com>

(No files)